Circuitry tested under the charged device model (CDM) is typically subjected to simulated electrostatic discharge (ESD) pulses using an automated CDM testing process. Failures may be investigated by continuously cycling components through a large, expensive automated CDM tester. This tedious process is often conducted for each type of CDM stress as failure analysis proceeds. The results are typically not subject to decomposition with respect to the condition and capabilities of major circuit nodes (e.g., power supply input, ground, etc.).
Transmission line pulse (TLP) testing methods have been developed, and can be used as a more finely-tuned mechanism to determine failure modes for individual nodes. However, TLP testing hardware is usually delicate and expensive. Thus, there is a need in the art for a less expensive apparatus, systems, and methods to conduct CDM testing, as well as to cross-check the results provided by automated CDM testing machines.